ARM: dts: omap3: fix DPLL4 M4 divider max value

The maximum divider value for DPLL4 M4 divider appears wrong. For most
OMAP3 family SoCs this is 16, but it is defined as 32, which is maybe
only valid for omap36xx. To avoid any overflows in trying to write this
register, set the max to 16 for all omap3 family, except omap36xx. For
omap36xx the maximum is set to 31, as it appears value 32 is not working
properly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Adam Ford <aford173@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index e66fc57ec35de277287f27aecd578b8aa29678ba..4e9cc9003594b5100477d71cb14d5056964f2353 100644 (file)
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -105,3 +105,7 @@ per_clkdm: per_clkdm {
                         <&mcbsp4_ick>, <&uart4_fck>;
        };
 };
+
+&dpll4_m4_ck {
+       ti,max-div = <31>;
+};

diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 685c82a9d03e49256803cd732013dfc8e5c7ce79..0656c32439d21cfb3b501f58c6b50ea0c3ee9ac5 100644 (file)
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -416,7 +416,7 @@ dpll4_m4_ck: dpll4_m4_ck@e40 {
                #clock-cells = <0>;
                compatible = "ti,divider-clock";
                clocks = <&dpll4_ck>;
-               ti,max-div = <32>;
+               ti,max-div = <16>;
                reg = <0x0e40>;
                ti,index-starts-at-one;
        };