ARM: dts: imx6ul: segin: Move ECSPI interface to board include file

The ECSPI interface is available on the expansion connector of every
PHYTEC phyBOARD-Segin. Move its definition to the board include file
for better reuse.

Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
index c6ef13685a7c910180ab3a443cf6014dbccb1248..32d90c67a6f2ac5561dd0d9475e3cf664613099e 100644 (file)
--- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
@@ -28,9 +28,6 @@ &tlv320 {
 };
 
 &ecspi3 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_ecspi3>;
-       cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
        status = "okay";
 };
 
@@ -93,14 +90,3 @@ &usbotg2 {
 &usdhc1 {
        status = "okay";
 };
-
-&iomuxc {
-       pinctrl_ecspi3: ecspi3grp {
-               fsl,pins = <
-                       MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO      0x10b0
-                       MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI      0x10b0
-                       MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK    0x10b0
-                       MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20     0x10b0
-               >;
-       };
-};

diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
index 7cd24ec40c36cf1bc33b002c62856eea667b5647..8d5f8dc6ad58cd9e303851261539d03ab740208a 100644 (file)
--- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
+++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi
@@ -103,6 +103,13 @@ &clks {
        assigned-clock-rates = <786432000>;
 };
 
+&ecspi3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi3>;
+       cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+       status = "disabled";
+};
+
 &fec2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet2>;
@@ -225,6 +232,15 @@ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03   0xb0
                >;
        };
 
+       pinctrl_ecspi3: ecspi3grp {
+               fsl,pins = <
+                       MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO      0x10b0
+                       MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI      0x10b0
+                       MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK    0x10b0
+                       MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20     0x10b0
+               >;
+       };
+
        pinctrl_enet2: enet2grp {
                fsl,pins = <
                        MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0