]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: imx51: Fix inconsistent display port names
authorMarco Franchi <marco.franchi@nxp.com>
Thu, 5 Oct 2017 14:31:41 +0000 (11:31 -0300)
committerShawn Guo <shawnguo@kernel.org>
Fri, 13 Oct 2017 07:58:42 +0000 (15:58 +0800)
Contrary to later i.MX SoCs, the parallel display interface pad groups on
i.MX51 are called DISP1 and DISP2 in the Reference Manual, not DISP0 and
DISP1.

Fix this inconsistence by changing the DISP names in the i.mx51 dts.

Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx51-apf51dev.dts
arch/arm/boot/dts/imx51-babbage.dts
arch/arm/boot/dts/imx51-ts4800.dts
arch/arm/boot/dts/imx51.dtsi

index f04d0df742781482396cde7e17cc03bf6daffbf7..2f1a9d203384bbdaf9d6375aab414df6f7e7162f 100644 (file)
@@ -51,7 +51,7 @@ lw700 {
 
                port {
                        display_in: endpoint {
-                               remote-endpoint = <&ipu_di0_disp0>;
+                               remote-endpoint = <&ipu_di0_disp1>;
                        };
                };
        };
@@ -218,6 +218,6 @@ MX51_PAD_DI1_PIN3__DI1_PIN3         0x5
        };
 };
 
-&ipu_di0_disp0 {
+&ipu_di0_disp1 {
        remote-endpoint = <&display_in>;
 };
index 297953cef0180b3c919ad680984f1567847c8916..668c37b76603218fcc5fb5af9c8edc70454c3d29 100644 (file)
@@ -39,7 +39,7 @@ clk_26M: codec_clock {
                };
        };
 
-       display0: disp0 {
+       display1: disp1 {
                compatible = "fsl,imx-parallel-display";
                interface-pix-fmt = "rgb24";
                pinctrl-names = "default";
@@ -61,12 +61,12 @@ timing0: dvi {
 
                port {
                        display0_in: endpoint {
-                               remote-endpoint = <&ipu_di0_disp0>;
+                               remote-endpoint = <&ipu_di0_disp1>;
                        };
                };
        };
 
-       display1: disp1 {
+       display2: disp2 {
                compatible = "fsl,imx-parallel-display";
                interface-pix-fmt = "rgb565";
                pinctrl-names = "default";
@@ -93,7 +93,7 @@ timing1: claawvga {
 
                port {
                        display1_in: endpoint {
-                               remote-endpoint = <&ipu_di1_disp1>;
+                               remote-endpoint = <&ipu_di1_disp2>;
                        };
                };
        };
@@ -348,11 +348,11 @@ sgtl5000: codec@0a {
        };
 };
 
-&ipu_di0_disp0 {
+&ipu_di0_disp1 {
        remote-endpoint = <&display0_in>;
 };
 
-&ipu_di1_disp1 {
+&ipu_di1_disp2 {
        remote-endpoint = <&display1_in>;
 };
 
index e6be869cfb8cfe6b0f8dd0aa8fd6edbf364d0eb0..35a11123cc9b9a9ee80fd92583cf492fc3ee04d7 100644 (file)
@@ -50,7 +50,7 @@ backlight: backlight {
                power-supply = <&backlight_reg>;
        };
 
-       display0: disp0 {
+       display1: disp1 {
                compatible = "fsl,imx-parallel-display";
                interface-pix-fmt = "rgb24";
                pinctrl-names = "default";
@@ -73,7 +73,7 @@ display-timings {
 
                port@0 {
                        display0_in: endpoint {
-                               remote-endpoint = <&ipu_di0_disp0>;
+                               remote-endpoint = <&ipu_di0_disp1>;
                        };
                };
        };
@@ -107,7 +107,7 @@ rtc: m41t00@68 {
        };
 };
 
-&ipu_di0_disp0 {
+&ipu_di0_disp1 {
        remote-endpoint = <&display0_in>;
 };
 
index 1ee1d542d9ad088c0bb94a55d66829d6ac1d92b9..378be720b3c7679992c9901ab710da85ae584b7d 100644 (file)
@@ -148,14 +148,14 @@ ipu: ipu@40000000 {
                        ipu_di0: port@2 {
                                reg = <2>;
 
-                               ipu_di0_disp0: endpoint {
+                               ipu_di0_disp1: endpoint {
                                };
                        };
 
                        ipu_di1: port@3 {
                                reg = <3>;
 
-                               ipu_di1_disp1: endpoint {
+                               ipu_di1_disp2: endpoint {
                                };
                        };
                };