]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
pinctrl: sunxi: Prepare for alternative bias voltage setting methods
authorOndrej Jirman <megous@megous.com>
Sat, 13 Apr 2019 16:54:12 +0000 (18:54 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Tue, 23 Apr 2019 10:29:21 +0000 (12:29 +0200)
H6 has a different I/O voltage bias setting method than A80. Prepare
existing code for using alternative bias voltage setting methods.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
drivers/pinctrl/sunxi/pinctrl-sunxi.c
drivers/pinctrl/sunxi/pinctrl-sunxi.h

index e05dd9a5551d470c12226bd44c1909a45c363640..a191a65217ac2e9dc344286d752ebe13c4d947a1 100644 (file)
@@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
        .pin_base = PL_BASE,
        .irq_banks = 2,
        .disable_strict_mode = true,
-       .has_io_bias_cfg = true,
+       .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
 };
 
 static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
index da37d594a13da813b6405fa371f6cae2c9b5cae8..0633a03d5e133484b65fd11728875faf861bd70e 100644 (file)
@@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
        .npins = ARRAY_SIZE(sun9i_a80_pins),
        .irq_banks = 5,
        .disable_strict_mode = true,
-       .has_io_bias_cfg = true,
+       .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
 };
 
 static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
index be04223591d46423327a2c871ef64fd1b1abea29..98c4de5f4019649abbcd8b3b57f53bc344e63d31 100644 (file)
@@ -617,7 +617,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
        u32 val, reg;
        int uV;
 
-       if (!pctl->desc->has_io_bias_cfg)
+       if (!pctl->desc->io_bias_cfg_variant)
                return 0;
 
        uV = regulator_get_voltage(supply);
@@ -628,25 +628,32 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
        if (uV == 0)
                return 0;
 
-       /* Configured value must be equal or greater to actual voltage */
-       if (uV <= 1800000)
-               val = 0x0; /* 1.8V */
-       else if (uV <= 2500000)
-               val = 0x6; /* 2.5V */
-       else if (uV <= 2800000)
-               val = 0x9; /* 2.8V */
-       else if (uV <= 3000000)
-               val = 0xA; /* 3.0V */
-       else
-               val = 0xD; /* 3.3V */
-
-       pin -= pctl->desc->pin_base;
-
-       reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
-       reg &= ~IO_BIAS_MASK;
-       writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
-
-       return 0;
+       switch (pctl->desc->io_bias_cfg_variant) {
+       case BIAS_VOLTAGE_GRP_CONFIG:
+               /*
+                * Configured value must be equal or greater to actual
+                * voltage.
+                */
+               if (uV <= 1800000)
+                       val = 0x0; /* 1.8V */
+               else if (uV <= 2500000)
+                       val = 0x6; /* 2.5V */
+               else if (uV <= 2800000)
+                       val = 0x9; /* 2.8V */
+               else if (uV <= 3000000)
+                       val = 0xA; /* 3.0V */
+               else
+                       val = 0xD; /* 3.3V */
+
+               pin -= pctl->desc->pin_base;
+
+               reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
+               reg &= ~IO_BIAS_MASK;
+               writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
+               return 0;
+       default:
+               return -EINVAL;
+       }
 }
 
 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
index ee15ab067b5fd0692e5ba4c010f1db1d88bd4d85..a62b813571362a55814656b33e3541c618380c90 100644 (file)
 #define PINCTRL_SUN7I_A20      BIT(7)
 #define PINCTRL_SUN8I_R40      BIT(8)
 
+enum sunxi_desc_bias_voltage {
+       BIAS_VOLTAGE_NONE,
+       /*
+        * Bias voltage configuration is done through
+        * Pn_GRP_CONFIG registers, as seen on A80 SoC.
+        */
+       BIAS_VOLTAGE_GRP_CONFIG,
+};
+
 struct sunxi_desc_function {
        unsigned long   variant;
        const char      *name;
@@ -117,7 +126,7 @@ struct sunxi_pinctrl_desc {
        const unsigned int              *irq_bank_map;
        bool                            irq_read_needs_mux;
        bool                            disable_strict_mode;
-       bool                            has_io_bias_cfg;
+       enum sunxi_desc_bias_voltage    io_bias_cfg_variant;
 };
 
 struct sunxi_pinctrl_function {