drm/i915/dsb: functions to enable/disable DSB engine.

DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.

v1: Initial version.
v2: POSTING_READ added after writing control register. (Shashank)
v3: cosmetic changes done. (Shashank)

Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190920115930.27829-7-animesh.manna@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 6000050b18a67394421df224e071c06f59fa9000..6fb4529689f1851bd0a9bf2f87191e3c9f529f86 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -26,6 +26,46 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb)
        return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
 }
 
+static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
+{
+       struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       enum pipe pipe = crtc->pipe;
+       u32 dsb_ctrl;
+
+       dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+       if (DSB_STATUS & dsb_ctrl) {
+               DRM_DEBUG_KMS("DSB engine is busy.\n");
+               return false;
+       }
+
+       dsb_ctrl |= DSB_ENABLE;
+       I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+       POSTING_READ(DSB_CTRL(pipe, dsb->id));
+       return true;
+}
+
+static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
+{
+       struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       enum pipe pipe = crtc->pipe;
+       u32 dsb_ctrl;
+
+       dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
+       if (DSB_STATUS & dsb_ctrl) {
+               DRM_DEBUG_KMS("DSB engine is busy.\n");
+               return false;
+       }
+
+       dsb_ctrl &= ~DSB_ENABLE;
+       I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl);
+
+       POSTING_READ(DSB_CTRL(pipe, dsb->id));
+       return true;
+}
+
 struct intel_dsb *
 intel_dsb_get(struct intel_crtc *crtc)
 {

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fba3e8b262965810c83c6787e5e3548c4ef19d2c..5fcbaaa8f3c61f806c1105eb229bfb18788f3593 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11703,6 +11703,7 @@ enum skl_power_gate {
 #define DSBSL_INSTANCE(pipe, id)       (_DSBSL_INSTANCE_BASE + \
                                         (pipe) * 0x1000 + (id) * 100)
 #define DSB_CTRL(pipe, id)             _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
+#define   DSB_ENABLE                   (1 << 31)
 #define   DSB_STATUS                   (1 << 0)
 
 #endif /* _I915_REG_H_ */