]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
ARM: dts: exynos: Rename Multi Core Timer node to "timer"
authorKrzysztof Kozlowski <krzk@kernel.org>
Mon, 23 Sep 2019 16:15:07 +0000 (18:15 +0200)
committerKrzysztof Kozlowski <krzk@kernel.org>
Wed, 2 Oct 2019 15:39:57 +0000 (17:39 +0200)
The device node name should reflect generic class of a device so rename
the Multi Core Timer node from "mct" to "timer".  This will be also in
sync with upcoming DT schema.  No functional change.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
arch/arm/boot/dts/exynos3250.dtsi
arch/arm/boot/dts/exynos4210.dtsi
arch/arm/boot/dts/exynos4412.dtsi
arch/arm/boot/dts/exynos5250.dtsi
arch/arm/boot/dts/exynos5260.dtsi
arch/arm/boot/dts/exynos54xx.dtsi

index 190d9160a5d16d18d7cd48b7d0fc91878329652d..06a1c7dd85edbde8d648de2148c1d3ba82982c45 100644 (file)
@@ -265,7 +265,7 @@ gic: interrupt-controller@10481000 {
                                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                };
 
-               mct@10050000 {
+               timer@10050000 {
                        compatible = "samsung,exynos4210-mct";
                        reg = <0x10050000 0x800>;
                        interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
index f220716239dbf06658c949e224acff26626b2565..6d3f19562aabbcfffa5c54ced68b6e1e281c108a 100644 (file)
@@ -106,7 +106,7 @@ l2c: l2-cache-controller@10502000 {
                        arm,data-latency = <2 2 1>;
                };
 
-               mct: mct@10050000 {
+               mct: timer@10050000 {
                        compatible = "samsung,exynos4210-mct";
                        reg = <0x10050000 0x800>;
                        interrupt-parent = <&mct_map>;
index d20db2dfe8e26d83fba590afcc6f9cd31f480bcc..8b6d5875c75d10580285af8a0aca404fd513227e 100644 (file)
@@ -243,7 +243,7 @@ isp_clock: clock-controller@10048000 {
                        clock-names = "aclk200", "aclk400_mcuisp";
                };
 
-               mct@10050000 {
+               timer@10050000 {
                        compatible = "samsung,exynos4412-mct";
                        reg = <0x10050000 0x800>;
                        interrupt-parent = <&mct_map>;
index 44fdaad68f7c3da274940177eedc40eda09930c6..4b43a4878096cfbdd286fc47d988409d5f8038c9 100644 (file)
@@ -233,7 +233,7 @@ clock_audss: audss-clock-controller@3810000 {
                        power-domains = <&pd_mau>;
                };
 
-               mct@101c0000 {
+               timer@101c0000 {
                        compatible = "samsung,exynos4210-mct";
                        reg = <0x101C0000 0x800>;
                        interrupt-controller;
index 3581b57fbbf7a4535d71fc4a723fd250a0215878..b0811dbbb362716bc04b3cc4ba29f62a7e1ad12c 100644 (file)
@@ -180,7 +180,7 @@ chipid: chipid@10000000 {
                        reg = <0x10000000 0x100>;
                };
 
-               mct: mct@100b0000 {
+               mct: timer@100b0000 {
                        compatible = "samsung,exynos4210-mct";
                        reg = <0x100B0000 0x1000>;
                        clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
index 02d34957cd836d655f05dd2ef83a3bc7282e96c5..ad7029bbfd4722ea881ddb2be4de7578a1df183c 100644 (file)
@@ -73,7 +73,7 @@ smp-sysram@53000 {
                        };
                };
 
-               mct: mct@101c0000 {
+               mct: timer@101c0000 {
                        compatible = "samsung,exynos4210-mct";
                        reg = <0x101c0000 0xb00>;
                        interrupt-parent = <&mct_map>;