amd/amdgpu: add sched array to IPs with multiple run-queues

This sched array can be passed on to entity creation routine
instead of manually creating such sched array on every context creation.

v2: squash in missing break fix

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 38ec5c919bd9e031110a76c6e31f1d28dad5e325..63f6365312d5d6467a07ddc21a7b495b20398973 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -74,7 +74,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
                           struct amdgpu_ctx *ctx)
 {
        unsigned num_entities = amdgpu_ctx_total_num_entities();
-       unsigned i, j, k;
+       unsigned i, j;
        int r;
 
        if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -121,73 +121,56 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
        ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
 
        for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
-               struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
-               struct drm_gpu_scheduler *sched_list[AMDGPU_MAX_RINGS];
-               unsigned num_rings = 0;
-               unsigned num_rqs = 0;
+               struct drm_gpu_scheduler **scheds;
+               struct drm_gpu_scheduler *sched;
+               unsigned num_scheds = 0;
 
                switch (i) {
                case AMDGPU_HW_IP_GFX:
-                       rings[0] = &adev->gfx.gfx_ring[0];
-                       num_rings = 1;
+                       scheds = adev->gfx.gfx_sched;
+                       num_scheds = 1;
                        break;
                case AMDGPU_HW_IP_COMPUTE:
-                       for (j = 0; j < adev->gfx.num_compute_rings; ++j)
-                               rings[j] = &adev->gfx.compute_ring[j];
-                       num_rings = adev->gfx.num_compute_rings;
+                       scheds = adev->gfx.compute_sched;
+                       num_scheds = adev->gfx.num_compute_sched;
                        break;
                case AMDGPU_HW_IP_DMA:
-                       for (j = 0; j < adev->sdma.num_instances; ++j)
-                               rings[j] = &adev->sdma.instance[j].ring;
-                       num_rings = adev->sdma.num_instances;
+                       scheds = adev->sdma.sdma_sched;
+                       num_scheds = adev->sdma.num_sdma_sched;
                        break;
                case AMDGPU_HW_IP_UVD:
-                       rings[0] = &adev->uvd.inst[0].ring;
-                       num_rings = 1;
+                       sched = &adev->uvd.inst[0].ring.sched;
+                       scheds = &sched;
+                       num_scheds = 1;
                        break;
                case AMDGPU_HW_IP_VCE:
-                       rings[0] = &adev->vce.ring[0];
-                       num_rings = 1;
+                       sched = &adev->vce.ring[0].sched;
+                       scheds = &sched;
+                       num_scheds = 1;
                        break;
                case AMDGPU_HW_IP_UVD_ENC:
-                       rings[0] = &adev->uvd.inst[0].ring_enc[0];
-                       num_rings = 1;
+                       sched = &adev->uvd.inst[0].ring_enc[0].sched;
+                       scheds = &sched;
+                       num_scheds = 1;
                        break;
                case AMDGPU_HW_IP_VCN_DEC:
-                       for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-                               if (adev->vcn.harvest_config & (1 << j))
-                                       continue;
-                               rings[num_rings++] = &adev->vcn.inst[j].ring_dec;
-                       }
+                       scheds = adev->vcn.vcn_dec_sched;
+                       num_scheds =  adev->vcn.num_vcn_dec_sched;
                        break;
                case AMDGPU_HW_IP_VCN_ENC:
-                       for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
-                               if (adev->vcn.harvest_config & (1 << j))
-                                       continue;
-                               for (k = 0; k < adev->vcn.num_enc_rings; ++k)
-                                       rings[num_rings++] = &adev->vcn.inst[j].ring_enc[k];
-                       }
+                       scheds = adev->vcn.vcn_enc_sched;
+                       num_scheds =  adev->vcn.num_vcn_enc_sched;
                        break;
                case AMDGPU_HW_IP_VCN_JPEG:
-                       for (j = 0; j < adev->jpeg.num_jpeg_inst; ++j) {
-                               if (adev->jpeg.harvest_config & (1 << j))
-                                       continue;
-                               rings[num_rings++] = &adev->jpeg.inst[j].ring_dec;
-                       }
+                       scheds = adev->jpeg.jpeg_sched;
+                       num_scheds =  adev->jpeg.num_jpeg_sched;
                        break;
                }
 
-               for (j = 0; j < num_rings; ++j) {
-                       if (!rings[j]->adev)
-                               continue;
-
-                       sched_list[num_rqs++] = &rings[j]->sched;
-               }
-
                for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j)
                        r = drm_sched_entity_init(&ctx->entities[i][j].entity,
-                                                 priority, sched_list,
-                                                 num_rqs, &ctx->guilty);
+                                                 priority, scheds,
+                                                 num_scheds, &ctx->guilty);
                if (r)
                        goto error_cleanup_entities;
        }
@@ -628,3 +611,45 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
        idr_destroy(&mgr->ctx_handles);
        mutex_destroy(&mgr->lock);
 }
+
+void amdgpu_ctx_init_sched(struct amdgpu_device *adev)
+{
+       int i, j;
+
+       for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
+               adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched;
+               adev->gfx.num_gfx_sched++;
+       }
+
+       for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+               adev->gfx.compute_sched[i] = &adev->gfx.compute_ring[i].sched;
+               adev->gfx.num_compute_sched++;
+       }
+
+       for (i = 0; i < adev->sdma.num_instances; i++) {
+               adev->sdma.sdma_sched[i] = &adev->sdma.instance[i].ring.sched;
+               adev->sdma.num_sdma_sched++;
+       }
+
+       for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+               if (adev->vcn.harvest_config & (1 << i))
+                       continue;
+               adev->vcn.vcn_dec_sched[adev->vcn.num_vcn_dec_sched++] =
+                       &adev->vcn.inst[i].ring_dec.sched;
+       }
+
+       for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+               if (adev->vcn.harvest_config & (1 << i))
+                       continue;
+               for (j = 0; j < adev->vcn.num_enc_rings; ++j)
+                       adev->vcn.vcn_enc_sched[adev->vcn.num_vcn_enc_sched++] =
+                               &adev->vcn.inst[i].ring_enc[j].sched;
+       }
+
+       for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
+               if (adev->jpeg.harvest_config & (1 << i))
+                       continue;
+               adev->jpeg.jpeg_sched[adev->jpeg.num_jpeg_sched++] =
+                       &adev->jpeg.inst[i].ring_dec.sched;
+       }
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
index da808633732b18a1ff3c9eff4ed8ff4c31bcb8ce..4ad90a44dc3cd36ffbee9361af04283366c7dee1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h
@@ -87,4 +87,7 @@ void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
 
+void amdgpu_ctx_init_sched(struct amdgpu_device *adev);
+
+
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index db91663df4f6c026292146a5d91ddd27734a9ad3..e1f8b715301a94cd3052249c5492ae7a23d2b19c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3036,6 +3036,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
                        adev->gfx.config.max_cu_per_sh,
                        adev->gfx.cu_info.number);
 
+       amdgpu_ctx_init_sched(adev);
+
        adev->accel_working = true;
 
        amdgpu_vm_check_compute_bug(adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 0ae0a2715b0d407000bb396664174fa6259bd6f6..8e88e0411662ebdb3d1b496af87201077ed45e91 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -269,8 +269,12 @@ struct amdgpu_gfx {
        bool                            me_fw_write_wait;
        bool                            cp_fw_write_wait;
        struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
+       struct drm_gpu_scheduler        *gfx_sched[AMDGPU_MAX_GFX_RINGS];
+       uint32_t                        num_gfx_sched;
        unsigned                        num_gfx_rings;
        struct amdgpu_ring              compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
+       struct drm_gpu_scheduler        *compute_sched[AMDGPU_MAX_COMPUTE_RINGS];
+       uint32_t                        num_compute_sched;
        unsigned                        num_compute_rings;
        struct amdgpu_irq_src           eop_irq;
        struct amdgpu_irq_src           priv_reg_irq;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
index 5131a0a1bc8aa90c8c9dde5482ff466ee0ce8977..bd9ef9cc86deae6c7183a6ccab20a33dbb869cce 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -43,6 +43,8 @@ struct amdgpu_jpeg {
        uint8_t num_jpeg_inst;
        struct amdgpu_jpeg_inst inst[AMDGPU_MAX_JPEG_INSTANCES];
        struct amdgpu_jpeg_reg internal;
+       struct drm_gpu_scheduler *jpeg_sched[AMDGPU_MAX_JPEG_INSTANCES];
+       uint32_t num_jpeg_sched;
        unsigned harvest_config;
        struct delayed_work idle_work;
        enum amd_powergating_state cur_state;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
index 761ff8be63147559621219d13a4d25ba30a70024..346dcb1f7146096568d3f5fb4631ca3760032725 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
@@ -52,6 +52,8 @@ struct amdgpu_sdma_instance {
 
 struct amdgpu_sdma {
        struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
+       struct drm_gpu_scheduler    *sdma_sched[AMDGPU_MAX_SDMA_INSTANCES];
+       uint32_t                    num_sdma_sched;
        struct amdgpu_irq_src   trap_irq;
        struct amdgpu_irq_src   illegal_inst_irq;
        struct amdgpu_irq_src   ecc_irq;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 3484ead6204690cec304aeef50e168f96b2bd792..e6dee8224d33771eb8f6edaab3c56656019bb09a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -31,6 +31,7 @@
 #define AMDGPU_VCN_MAX_ENC_RINGS       3
 
 #define AMDGPU_MAX_VCN_INSTANCES       2
+#define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES
 
 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
@@ -189,8 +190,12 @@ struct amdgpu_vcn {
        uint32_t                *dpg_sram_curr_addr;
 
        uint8_t num_vcn_inst;
-       struct amdgpu_vcn_inst  inst[AMDGPU_MAX_VCN_INSTANCES];
-       struct amdgpu_vcn_reg   internal;
+       struct amdgpu_vcn_inst   inst[AMDGPU_MAX_VCN_INSTANCES];
+       struct amdgpu_vcn_reg    internal;
+       struct drm_gpu_scheduler *vcn_enc_sched[AMDGPU_MAX_VCN_ENC_RINGS];
+       struct drm_gpu_scheduler *vcn_dec_sched[AMDGPU_MAX_VCN_INSTANCES];
+       uint32_t                 num_vcn_enc_sched;
+       uint32_t                 num_vcn_dec_sched;
 
        unsigned        harvest_config;
        int (*pause_dpg_mode)(struct amdgpu_device *adev,