]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
MIPS: If KVM is enabled then use the KVM specific routine to flush the TLBs on a...
authorSanjay Lal <sanjayl@kymasys.com>
Thu, 22 Nov 2012 02:34:11 +0000 (18:34 -0800)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 8 May 2013 01:55:36 +0000 (03:55 +0200)
Signed-off-by: Sanjay Lal <sanjayl@kymasys.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mmu_context.h

index e81d719efcd18e9e226d07e8d69e29b970c89280..c42562d801c5093636c075e72aa7884ab0f20e67 100644 (file)
@@ -106,15 +106,21 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 static inline void
 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
 {
+       extern void kvm_local_flush_tlb_all(void);
        unsigned long asid = asid_cache(cpu);
 
        if (! ((asid += ASID_INC) & ASID_MASK) ) {
                if (cpu_has_vtag_icache)
                        flush_icache_all();
+#ifdef CONFIG_VIRTUALIZATION
+               kvm_local_flush_tlb_all();      /* start new asid cycle */
+#else
                local_flush_tlb_all();  /* start new asid cycle */
+#endif
                if (!asid)              /* fix version if needed */
                        asid = ASID_FIRST_VERSION;
        }
+
        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
 }