drm/exynos: Properly report supported formats for each device

Exynos DRM reported that all planes for all supported sub-devices supports
only three pixel formats: XRGB24, ARGB24 and NV12. This patch lets each
Exynos DRM sub-drivers to provide the list of supported pixel formats
and registers this list to DRM core.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index f24dc2d2e870a192b7e3ecdd05b726f2e4001bbb..b3c730770b0f07e4cf3885ceb2939eae062ff6bd 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -54,6 +54,13 @@ static const char * const decon_clks_name[] = {
        "sclk_decon_eclk",
 };
 
+static const uint32_t decon_formats[] = {
+       DRM_FORMAT_XRGB1555,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+};
+
 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
 {
        struct decon_context *ctx = crtc->ctx;
@@ -497,7 +504,8 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
                                                        DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                               1 << ctx->pipe, type, zpos);
+                               1 << ctx->pipe, type, decon_formats,
+                               ARRAY_SIZE(decon_formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index c74e30e34c13489441bd452ae6e927d9475d193c..cbdb78ef3baca57cd1ddf701425b953f140377f2 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -70,6 +70,18 @@ static const struct of_device_id decon_driver_dt_match[] = {
 };
 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
 
+static const uint32_t decon_formats[] = {
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_RGBX8888,
+       DRM_FORMAT_BGRX8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_RGBA8888,
+       DRM_FORMAT_BGRA8888,
+};
+
 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
 {
        struct decon_context *ctx = crtc->ctx;
@@ -693,7 +705,8 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, decon_formats,
+                                       ARRAY_SIZE(decon_formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index d96044f4c2287977ac07f821e25266a44f583cea..750a9e6b9e8d92c312e3bb685fb524f249ad0488 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -188,6 +188,14 @@ static const struct of_device_id fimd_driver_dt_match[] = {
 };
 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 
+static const uint32_t fimd_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_XRGB1555,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+};
+
 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
        struct platform_device *pdev)
 {
@@ -956,7 +964,8 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, fimd_formats,
+                                       ARRAY_SIZE(fimd_formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index fad7dfc7a7786c1588d3658eda50e1582997a3c2..865d6eb0c8458e4f5e7f6df80ec5e1d495d9db69 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -20,12 +20,6 @@
 #include "exynos_drm_gem.h"
 #include "exynos_drm_plane.h"
 
-static const uint32_t formats[] = {
-       DRM_FORMAT_XRGB8888,
-       DRM_FORMAT_ARGB8888,
-       DRM_FORMAT_NV12,
-};
-
 /*
  * This function is to get X or Y size shown via screen. This needs length and
  * start position of CRTC.
@@ -217,13 +211,14 @@ static void exynos_plane_attach_zpos_property(struct drm_plane *plane,
 int exynos_plane_init(struct drm_device *dev,
                      struct exynos_drm_plane *exynos_plane,
                      unsigned long possible_crtcs, enum drm_plane_type type,
+                     const uint32_t *formats, unsigned int fcount,
                      unsigned int zpos)
 {
        int err;
 
        err = drm_universal_plane_init(dev, &exynos_plane->base, possible_crtcs,
-                                      &exynos_plane_funcs, formats,
-                                      ARRAY_SIZE(formats), type);
+                                      &exynos_plane_funcs, formats, fcount,
+                                      type);
        if (err) {
                DRM_ERROR("failed to initialize plane\n");
                return err;

diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h b/drivers/gpu/drm/exynos/exynos_drm_plane.h
index 8c88ae983c38c5220203f901e7afe2952f65f725..476c9340b591cb107f6fc66f4dde0e0da217c49f 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h
@@ -12,4 +12,5 @@
 int exynos_plane_init(struct drm_device *dev,
                      struct exynos_drm_plane *exynos_plane,
                      unsigned long possible_crtcs, enum drm_plane_type type,
+                     const uint32_t *formats, unsigned int fcount,
                      unsigned int zpos);

diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index b6d00ddb6dd6bff7b5d2b271b24dbbeae073c831..75718e1bc3dd29eb41df43b43922548c77240b4c 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -83,6 +83,12 @@ static const char fake_edid_info[] = {
        0x00, 0x00, 0x00, 0x06
 };
 
+static const uint32_t formats[] = {
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_NV12,
+};
+
 static int vidi_enable_vblank(struct exynos_drm_crtc *crtc)
 {
        struct vidi_context *ctx = crtc->ctx;
@@ -443,7 +449,8 @@ static int vidi_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, formats,
+                                       ARRAY_SIZE(formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index d7e781153cff32c609827db3d8855c8378b2c7c5..7f81cce966d4b49e17516cbc76c1974124fa1b65 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -43,6 +43,7 @@
 
 #define MIXER_WIN_NR           3
 #define MIXER_DEFAULT_WIN      0
+#define VP_DEFAULT_WIN         2
 
 /* The pixelformats that are natively supported by the mixer. */
 #define MXR_FORMAT_RGB565      4
@@ -74,6 +75,19 @@ enum mixer_flag_bits {
        MXR_BIT_VSYNC,
 };
 
+static const uint32_t mixer_formats[] = {
+       DRM_FORMAT_XRGB4444,
+       DRM_FORMAT_XRGB1555,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+};
+
+static const uint32_t vp_formats[] = {
+       DRM_FORMAT_NV12,
+       DRM_FORMAT_NV21,
+};
+
 struct mixer_context {
        struct platform_device *pdev;
        struct device           *dev;
@@ -1171,7 +1185,6 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
        struct mixer_context *ctx = dev_get_drvdata(dev);
        struct drm_device *drm_dev = data;
        struct exynos_drm_plane *exynos_plane;
-       enum drm_plane_type type;
        unsigned int zpos;
        int ret;
 
@@ -1180,10 +1193,23 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
                return ret;
 
        for (zpos = 0; zpos < MIXER_WIN_NR; zpos++) {
+               enum drm_plane_type type;
+               const uint32_t *formats;
+               unsigned int fcount;
+
                type = (zpos == MIXER_DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
+               if (zpos < VP_DEFAULT_WIN) {
+                       formats = mixer_formats;
+                       fcount = ARRAY_SIZE(mixer_formats);
+               } else {
+                       formats = vp_formats;
+                       fcount = ARRAY_SIZE(vp_formats);
+               }
+
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, formats, fcount,
+                                       zpos);
                if (ret)
                        return ret;
        }