]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: dts: renesas: r8a7796: Update OPPs to support CA53 dfs
authorDien Pham <dien.pham.ry@renesas.com>
Mon, 29 Jan 2018 18:21:20 +0000 (19:21 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Tue, 13 Mar 2018 18:05:26 +0000 (19:05 +0100)
Describe frequencies, other than the default for CA53 cores.  This is a
pre-requisite for using providing alternative frequencies for use with
CPUFreq with these cores.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a7796.dtsi

index 157bd28014ed0e1faaeb50e5a515ccaa5c423cc5..076a9c9346aeb1ec01a6a65d16ccedad2bf42e85 100644 (file)
@@ -204,11 +204,27 @@ cluster1_opp: opp_table1 {
                compatible = "operating-points-v2";
                opp-shared;
 
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
                opp-1200000000 {
                        opp-hz = /bits/ 64 <1200000000>;
                        opp-microvolt = <820000>;
                        clock-latency-ns = <300000>;
                };
+               opp-1300000000 {
+                       opp-hz = /bits/ 64 <1300000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+                       turbo-mode;
+               };
        };
 
        /* External PCIe clock - can be overridden by the board */