]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
clk: pxa: export 32kHz PLL
authorRobert Jarzmik <robert.jarzmik@free.fr>
Wed, 27 Jun 2018 19:41:23 +0000 (21:41 +0200)
committerStephen Boyd <sboyd@kernel.org>
Fri, 6 Jul 2018 20:52:57 +0000 (13:52 -0700)
This clock is especially used by the RTC driver, so export it so that
devicetree users can use it.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/pxa/clk-pxa25x.c
drivers/clk/pxa/clk-pxa27x.c
drivers/clk/pxa/clk-pxa3xx.c
include/dt-bindings/clock/pxa-clock.h

index 6416c1f8e6324915e662fc4a41e946f0d478d513..e88f8e01fe3a6d237f2cf05dfc9dcc5dbbd81f53 100644 (file)
@@ -292,8 +292,10 @@ static void __init pxa25x_register_plls(void)
 {
        clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
                                CLK_GET_RATE_NOCACHE, 3686400);
-       clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
-                               CLK_GET_RATE_NOCACHE, 32768);
+       clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
+                           clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
+                                                   CLK_GET_RATE_NOCACHE,
+                                                   32768));
        clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
        clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
                                  0, 26, 1);
index 25a30194d27a390a950667c41a9caff4f7ae16b0..d40b63e7bbce906850e2628c47c77b0836742209 100644 (file)
@@ -314,9 +314,10 @@ static void __init pxa27x_register_plls(void)
        clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
                                CLK_GET_RATE_NOCACHE,
                                13 * MHz);
-       clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
-                               CLK_GET_RATE_NOCACHE,
-                               32768 * KHz);
+       clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
+                           clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
+                                                   CLK_GET_RATE_NOCACHE,
+                                                   32768 * KHz));
        clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
        clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
 }
index 2d126df2bccd4639897122e0672c1ba45a870b1e..7aa120c3bd085bfe18f6a4d1b6bf693a6f5211aa 100644 (file)
@@ -286,9 +286,10 @@ static void __init pxa3xx_register_plls(void)
        clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
                                CLK_GET_RATE_NOCACHE,
                                13 * MHz);
-       clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
-                               CLK_GET_RATE_NOCACHE,
-                               32768);
+       clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
+                           clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
+                                                   CLK_GET_RATE_NOCACHE,
+                                                   32768));
        clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL,
                                CLK_GET_RATE_NOCACHE,
                                120 * MHz);
index e65803b1dc7ea6a44f50d92a9b0a938a7b6ec9a8..0b0fd2b015389f0c4911aca6d97a0032ca0f6f98 100644 (file)
@@ -72,6 +72,7 @@
 #define CLK_USIM 58
 #define CLK_USIM1 59
 #define CLK_USMI0 60
-#define CLK_MAX 61
+#define CLK_OSC32k768 61
+#define CLK_MAX 62
 
 #endif