arm64: dts: ls1012a: Add PCIe controller DT node

Add PCIe controller node for ls1012a platform.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index a7698ac7264b01e2d7cd26bf048beef94c0ecc14..fe1ea5d707a8f7ec3dc0af3e66c05dd754f7528b 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -478,5 +478,29 @@ msi: msi-controller1@1572000 {
                        msi-controller;
                        interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
                };
+
+               pcie@3400000 {
+                       compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+                              0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg-names = "regs", "config";
+                       interrupts = <0 118 0x4>, /* controller interrupt */
+                                    <0 117 0x4>; /* PME interrupt */
+                       interrupt-names = "aer", "pme";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       num-lanes = <4>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                       msi-parent = <&msi>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
+               };
        };
 };