]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
dt-bindings/irq: Add binding for Freescale IRQSTEER multiplexer
authorLucas Stach <l.stach@pengutronix.de>
Mon, 17 Dec 2018 14:01:19 +0000 (15:01 +0100)
committerMarc Zyngier <marc.zyngier@arm.com>
Tue, 18 Dec 2018 15:36:57 +0000 (15:36 +0000)
This adds the DT binding for the Freescale IRQSTEER interrupt
multiplexer found in the i.MX8 familiy SoCs.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.txt
new file mode 100644 (file)
index 0000000..45790ce
--- /dev/null
@@ -0,0 +1,34 @@
+Freescale IRQSTEER Interrupt multiplexer
+
+Required properties:
+
+- compatible: should be:
+       - "fsl,imx8m-irqsteer"
+       - "fsl,imx-irqsteer"
+- reg: Physical base address and size of registers.
+- interrupts: Should contain the parent interrupt line used to multiplex the
+  input interrupts.
+- clocks: Should contain one clock for entry in clock-names
+  see Documentation/devicetree/bindings/clock/clock-bindings.txt
+- clock-names:
+   - "ipg": main logic clock
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source. The value must be 1.
+- fsl,channel: The output channel that all input IRQs should be steered into.
+- fsl,irq-groups: Number of IRQ groups managed by this controller instance.
+  Each group manages 64 input interrupts.
+
+Example:
+
+       interrupt-controller@32e2d000 {
+               compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
+               reg = <0x32e2d000 0x1000>;
+               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+               clock-names = "ipg";
+               fsl,channel = <0>;
+               fsl,irq-groups = <1>;
+               interrupt-controller;
+               #interrupt-cells = <1>;
+       };