From: Graeme Gregory Date: Fri, 4 Aug 2017 21:49:44 +0000 (+0100) Subject: ACPI: SPCR: work around clock issue on xgene UART X-Git-Tag: v4.14-rc1~138^2~1^4 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=03c3876f2e3b4c79ced7d1d227e5a7fe645ed666;p=linux.git ACPI: SPCR: work around clock issue on xgene UART xgene v1/v2 8250 UARTs don't run at the standard clock rate expected by the driver and there is no information on clocking available from the SPCR table. As there has been no progress on relevant vendors updating DBG2/SPCR specifications to fix this work around this using the previous xgene quirk handling to avoid setting a baud rate and therefore using the UART as configured by firmware. Signed-off-by: Graeme Gregory Tested-by: Mark Salter Reviewed-by: Mark Salter Signed-off-by: Rafael J. Wysocki --- diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index 2c156941b371..40a56b538b9f 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -188,11 +188,19 @@ int __init parse_spcr(bool earlycon) uart = "qdf2400_e44"; } - if (xgene_8250_erratum_present(table)) + if (xgene_8250_erratum_present(table)) { iotype = "mmio32"; - snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, - table->serial_port.address, baud_rate); + /* for xgene v1 and v2 we don't know the clock rate of the + * UART so don't attempt to change to the baud rate state + * in the table because driver cannot calculate the dividers + */ + snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype, + table->serial_port.address); + } else { + snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, + table->serial_port.address, baud_rate); + } pr_info("console: %s\n", opts);