From: Takeshi Kihara Date: Fri, 4 Nov 2016 13:58:07 +0000 (+0100) Subject: clk: renesas: r8a7795: Fix HDMI parent clock X-Git-Tag: v4.10-rc1~161^2~28^2~3 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=0a30284b9fe19780d4587e74578e460469d88706;p=linux.git clk: renesas: r8a7795: Fix HDMI parent clock Correct HDMI parent clock so that the rate of the HDMI clock is 1/4 rather than 1/2 of the rate of PLL1 as per the v0.52 (Jun, 15) manual. Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 726c3d7940b4..50698a7d9074 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -98,7 +98,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014), - DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250), + DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250), DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),