From: Catalin Marinas <catalin.marinas@arm.com>
Date: Thu, 19 Dec 2013 17:57:51 +0000 (+0000)
Subject: Merge tag 'arm64-suspend' of git://linux-arm.org/linux-2.6-lp into upstream
X-Git-Tag: v3.14-rc1~153^2~11
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=0a5be743e8c3c3230600fbc0cf923fb5dbefd579;p=linux.git

Merge tag 'arm64-suspend' of git://linux-arm.org/linux-2.6-lp into upstream

* tag 'arm64-suspend' of git://linux-arm.org/linux-2.6-lp:
  arm64: add CPU power management menu/entries
  arm64: kernel: add PM build infrastructure
  arm64: kernel: add CPU idle call
  arm64: enable generic clockevent broadcast
  arm64: kernel: implement HW breakpoints CPU PM notifier
  arm64: kernel: refactor code to install/uninstall breakpoints
  arm: kvm: implement CPU PM notifier
  arm64: kernel: implement fpsimd CPU PM notifier
  arm64: kernel: cpu_{suspend/resume} implementation
  arm64: kernel: suspend/resume registers save/restore
  arm64: kernel: build MPIDR_EL1 hash function data structure
  arm64: kernel: add MPIDR_EL1 accessors macros

Conflicts:
	arch/arm64/Kconfig
---

0a5be743e8c3c3230600fbc0cf923fb5dbefd579
diff --cc arch/arm64/Kconfig
index 101683d336c9,99589e782834..249acb9da4e3
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@@ -11,8 -12,9 +12,10 @@@ config ARM6
  	select BUILDTIME_EXTABLE_SORT
  	select CLONE_BACKWARDS
  	select COMMON_CLK
+ 	select CPU_PM if (SUSPEND || CPU_IDLE)
 +	select DCACHE_WORD_ACCESS
  	select GENERIC_CLOCKEVENTS
+ 	select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  	select GENERIC_IOMAP
  	select GENERIC_IRQ_PROBE
  	select GENERIC_IRQ_SHOW
diff --cc arch/arm64/include/asm/cputype.h
index e1af1b4200d5,e371936b8ab2..c404fb0df3a6
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@@ -20,9 -30,19 +20,19 @@@
  
  #define MPIDR_HWID_BITMASK	0xff00ffffff
  
+ #define MPIDR_LEVEL_BITS_SHIFT	3
+ #define MPIDR_LEVEL_BITS	(1 << MPIDR_LEVEL_BITS_SHIFT)
+ #define MPIDR_LEVEL_MASK	((1 << MPIDR_LEVEL_BITS) - 1)
+ 
+ #define MPIDR_LEVEL_SHIFT(level) \
+ 	(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
+ 
+ #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
+ 	((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
+ 
  #define read_cpuid(reg) ({						\
  	u64 __val;							\
 -	asm("mrs	%0, " reg : "=r" (__val));			\
 +	asm("mrs	%0, " #reg : "=r" (__val));			\
  	__val;								\
  })