From: Stefan Agner Date: Tue, 2 Dec 2014 17:11:59 +0000 (+0100) Subject: ARM: dts: vf610: add system reset controller and syscon-reboot X-Git-Tag: v4.0-rc1~69^2~19^2~16 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=0d018d7387bd3c2d25ca7ed1a6b3631c071cd918;p=linux.git ARM: dts: vf610: add system reset controller and syscon-reboot Add the system reset controller (SRC) module and use syscon-reboot to register a restart handler which restarts the SoC using the SRC SW_RST bit. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index ea0f74f6eeb3..29016090d060 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -130,6 +130,10 @@ &sai2 { interrupts = ; }; +&src { + interrupts = ; +}; + &uart0 { interrupts = ; }; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 712646814cc6..a55e1f9a414d 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -43,6 +43,13 @@ sxosc: sxosc { clock-frequency = <32768>; }; + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&src>; + offset = <0x0>; + mask = <0x1000>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -318,6 +325,11 @@ usbmisc0: usb@40034800 { clocks = <&clks VF610_CLK_USBC0>; status = "disabled"; }; + + src: src@4006e000 { + compatible = "fsl,vf610-src", "syscon"; + reg = <0x4006e000 0x1000>; + }; }; aips1: aips-bus@40080000 {