From: Hoath, Nicholas <nicholas.hoath@intel.com>
Date: Thu, 5 Feb 2015 10:47:24 +0000 (+0000)
Subject: drm/i915/gen9: Implement WaForceEnableNonCoherent
X-Git-Tag: v4.1-rc1~69^2~35^2~62
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=13bea49c8b203b0d2eb789c6f91c03de4e09cf4d;p=linux.git

drm/i915/gen9: Implement WaForceEnableNonCoherent

v2: Don't add WaHdcDisableFetchWhenMasked. Add stepping check for
WaForceEnableNonCoherent

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e35b341c3cef..573b80f0c153 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -902,6 +902,17 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 				  GEN9_ENABLE_YV12_BUGFIX);
 	}
 
+	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
+		/*
+		 *Use Force Non-Coherent whenever executing a 3D context. This
+		 * is a workaround for a possible hang in the unlikely event
+		 * a TLB invalidation occurs during a PSD flush.
+		 */
+		/* WaForceEnableNonCoherent:skl */
+		WA_SET_BIT_MASKED(HDC_CHICKEN0,
+				  HDC_FORCE_NON_COHERENT);
+	}
+
 	/* Wa4x4STCOptimizationDisable:skl */
 	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);