From: Andrew Jiang Date: Tue, 21 Nov 2017 20:59:42 +0000 (-0500) Subject: drm/amd/display: Refine update flags usage in update_dchubp_dpp X-Git-Tag: v4.16-rc1~96^2~19^2~102 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=16a29dd3bb18ea23d9676e6a3b1c6464dba620c3;p=linux.git drm/amd/display: Refine update flags usage in update_dchubp_dpp - Only update DPP clock if it's a full update. - Program viewport on position change. This caused SLS regressions. Signed-off-by: Andrew Jiang Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e9ecbcb66e80..7846534cd6d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1726,7 +1726,7 @@ static void update_dchubp_dpp( union plane_size size = plane_state->plane_size; /* depends on DML calculation, DPP clock value may change dynamically */ - if (pipe_ctx->plane_state->update_flags.raw != 0) { + if (plane_state->update_flags.bits.full_update) { enable_dppclk( dc->hwseq, pipe_ctx->pipe_idx, @@ -1770,7 +1770,8 @@ static void update_dchubp_dpp( } if (plane_state->update_flags.bits.full_update || - plane_state->update_flags.bits.scaling_change) { + plane_state->update_flags.bits.scaling_change || + plane_state->update_flags.bits.position_change) { hubp->funcs->mem_program_viewport( hubp, &pipe_ctx->plane_res.scl_data.viewport,