From: Alexander Shiyan <shc_work@mail.ru>
Date: Sat, 26 Apr 2014 04:52:07 +0000 (+0400)
Subject: ARM: dts: imx27-phytec-phycore-som: Fix active level for FEC reset
X-Git-Tag: v3.16-rc1~30^2~41^2~20^2~26
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=198e31d08bd3caeb58c54232f1a06a9097715158;p=linux.git

ARM: dts: imx27-phytec-phycore-som: Fix active level for FEC reset

FEC reset GPIO is active low. Fix this typo.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
---

diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 32cc7dac9ab6..93482e9d2c93 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -182,7 +182,7 @@ pwgt1spi_reg: pwgt1spi {
 
 &fec {
 	phy-mode = "mii";
-	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
 	phy-supply = <&reg_3v3>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;