From: Maxime Ripard <maxime.ripard@free-electrons.com>
Date: Mon, 24 Feb 2014 16:29:06 +0000 (+0100)
Subject: ARM: sun6i: dt: Fix mod0 compatible
X-Git-Tag: v3.15-rc1~77^2~29^2
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=225b02163cd51b6d5ebef4d2e19a09345f2ee3a5;p=linux.git

ARM: sun6i: dt: Fix mod0 compatible

The module 0 clock compatibles were changed between the time the patch was sent
and it was merged. Update the compatibles.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index af6f87c4e1c7..42f310a925c4 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -200,7 +200,7 @@ apb2_gates: clk@01c2006c {
 
 		spi0_clk: clk@01c200a0 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-mod0-clk";
+			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a0 0x4>;
 			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi0";
@@ -208,7 +208,7 @@ spi0_clk: clk@01c200a0 {
 
 		spi1_clk: clk@01c200a4 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-mod0-clk";
+			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a4 0x4>;
 			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi1";
@@ -216,7 +216,7 @@ spi1_clk: clk@01c200a4 {
 
 		spi2_clk: clk@01c200a8 {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-mod0-clk";
+			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200a8 0x4>;
 			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi2";
@@ -224,7 +224,7 @@ spi2_clk: clk@01c200a8 {
 
 		spi3_clk: clk@01c200ac {
 			#clock-cells = <0>;
-			compatible = "allwinner,sun4i-mod0-clk";
+			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c200ac 0x4>;
 			clocks = <&osc24M>, <&pll6>;
 			clock-output-names = "spi3";