From: Ville Syrjälä Date: Fri, 18 Aug 2017 18:37:05 +0000 (+0300) Subject: drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x X-Git-Tag: v4.15-rc1~90^2~40^2~70 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=309bd8ed464fc08f79152e4a18b1da2b11410842;p=linux.git drm/i915: Reinstate GMBUS and AUX interrupts on gen4/g4x Now that we're not using MSI anymore on gen4 we can start using GMBUS and AUX interrupts again. These were disabled on account of them causing the hardware to somehow generate legacy interrupts even when MSI was enabled. See commit c12aba5aa0e6 ("drm/i915: stop using GMBUS IRQs on Gen4 chips") and commit 4e6b788c3f23 ("drm/i915: Disable dp aux irq on g4x") for more details. Cc: Daniel Vetter Cc: Chris Wilson Cc: Jiri Kosina Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-17-ville.syrjala@linux.intel.com Acked-by: Chris Wilson --- diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5d379c89722c..a24659b5e6b5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -777,7 +777,6 @@ struct intel_csr { func(has_fpga_dbg); \ func(has_full_ppgtt); \ func(has_full_48bit_ppgtt); \ - func(has_gmbus_irq); \ func(has_gmch_display); \ func(has_guc); \ func(has_guc_ct); \ @@ -3095,9 +3094,12 @@ intel_info(const struct drm_i915_private *dev_priv) * even when in MSI mode. This results in spurious interrupt warnings if the * legacy irq no. is shared with another device. The kernel then disables that * interrupt source and so prevents the other device from working properly. + * + * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX + * interrupts. */ -#define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5) -#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq) +#define HAS_AUX_IRQ(dev_priv) true +#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 129877b94c20..853002fb0371 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -200,7 +200,6 @@ static const struct intel_device_info intel_gm45_info __initconst = { #define GEN5_FEATURES \ .gen = 5, .num_pipes = 2, \ .has_hotplug = 1, \ - .has_gmbus_irq = 1, \ .ring_mask = RENDER_RING | BSD_RING, \ .has_snoop = true, \ GEN_DEFAULT_PIPEOFFSETS, \ @@ -225,7 +224,6 @@ static const struct intel_device_info intel_ironlake_m_info __initconst = { .has_llc = 1, \ .has_rc6 = 1, \ .has_rc6p = 1, \ - .has_gmbus_irq = 1, \ .has_aliasing_ppgtt = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS @@ -268,7 +266,6 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst = .has_llc = 1, \ .has_rc6 = 1, \ .has_rc6p = 1, \ - .has_gmbus_irq = 1, \ .has_aliasing_ppgtt = 1, \ .has_full_ppgtt = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ @@ -321,7 +318,6 @@ static const struct intel_device_info intel_valleyview_info __initconst = { .has_psr = 1, .has_runtime_pm = 1, .has_rc6 = 1, - .has_gmbus_irq = 1, .has_gmch_display = 1, .has_hotplug = 1, .has_aliasing_ppgtt = 1, @@ -412,7 +408,6 @@ static const struct intel_device_info intel_cherryview_info __initconst = { .has_runtime_pm = 1, .has_resource_streamer = 1, .has_rc6 = 1, - .has_gmbus_irq = 1, .has_logical_ring_contexts = 1, .has_gmch_display = 1, .has_aliasing_ppgtt = 1, @@ -474,7 +469,6 @@ static const struct intel_device_info intel_skylake_gt4_info __initconst = { .has_resource_streamer = 1, \ .has_rc6 = 1, \ .has_dp_mst = 1, \ - .has_gmbus_irq = 1, \ .has_logical_ring_contexts = 1, \ .has_guc = 1, \ .has_aliasing_ppgtt = 1, \