From: Thierry Reding <treding@nvidia.com>
Date: Mon, 7 Jul 2014 13:35:06 +0000 (+0200)
Subject: drm/tegra: sor - Configure proper sync polarities
X-Git-Tag: v3.17-rc1~82^2~1^2~3
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=3f4f3b5fede02d338383619ff57744a8415ccceb;p=linux.git

drm/tegra: sor - Configure proper sync polarities

Program the sync signal polarities according to the display mode.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 479da1b210b4..6cb861bf1e03 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -815,12 +815,22 @@ static int tegra_output_sor_enable(struct tegra_output *output)
 	 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
 	 * raster, associate with display controller)
 	 */
-	value = SOR_STATE_ASY_VSYNCPOL |
-		SOR_STATE_ASY_HSYNCPOL |
-		SOR_STATE_ASY_PROTOCOL_DP_A |
+	value = SOR_STATE_ASY_PROTOCOL_DP_A |
 		SOR_STATE_ASY_CRC_MODE_COMPLETE |
 		SOR_STATE_ASY_OWNER(dc->pipe + 1);
 
+	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
+		value &= ~SOR_STATE_ASY_HSYNCPOL;
+
+	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+		value |= SOR_STATE_ASY_HSYNCPOL;
+
+	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+		value &= ~SOR_STATE_ASY_VSYNCPOL;
+
+	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
+		value |= SOR_STATE_ASY_VSYNCPOL;
+
 	switch (config.bits_per_pixel) {
 	case 24:
 		value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;