From: Ingo Molnar Date: Thu, 4 Sep 2008 11:02:35 +0000 (+0200) Subject: Merge branch 'linus' into x86/x2apic X-Git-Tag: v2.6.28-rc1~711^2^2~44^2~1^2~1 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=42390cdec5f6e6e2ee54f308474a6ef7dd16aa5c;p=linux.git Merge branch 'linus' into x86/x2apic Conflicts: arch/x86/kernel/cpu/cyrix.c include/asm-x86/cpufeature.h Signed-off-by: Ingo Molnar --- 42390cdec5f6e6e2ee54f308474a6ef7dd16aa5c diff --cc arch/x86/kernel/cpu/cyrix.c index db5868cd2443,e710a21bb6e8..ada50505a5c8 --- a/arch/x86/kernel/cpu/cyrix.c +++ b/arch/x86/kernel/cpu/cyrix.c @@@ -131,26 -131,9 +131,9 @@@ static void __cpuinit set_cx86_memwb(vo /* set 'Not Write-through' */ write_cr0(read_cr0() | X86_CR0_NW); /* CCR2 bit 2: lock NW bit and set WT1 */ - setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14); + setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14); } - static void __cpuinit set_cx86_inc(void) - { - unsigned char ccr3; - - printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n"); - - ccr3 = getCx86(CX86_CCR3); - setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ - /* PCR1 -- Performance Control */ - /* Incrementor on, whatever that is */ - setCx86_old(CX86_PCR1, getCx86_old(CX86_PCR1) | 0x02); - /* PCR0 -- Performance Control */ - /* Incrementor Margin 10 */ - setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) | 0x04); - setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ - } - /* * Configure later MediaGX and/or Geode processor. */ diff --cc include/asm-x86/cpufeature.h index 8d842af4cf7a,762f6a6bc707..c6845b94be84 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h @@@ -93,7 -91,7 +93,8 @@@ #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ + #define X86_FEATURE_XMM4_2 (4*32+20) /* Streaming SIMD Extensions-4.2 */ +#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */ @@@ -192,7 -190,7 +193,8 @@@ extern const char * const x86_power_fla #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) + #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) +#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) # define cpu_has_invlpg 1