From: Jisheng Zhang <jszhang@marvell.com>
Date: Thu, 12 Jun 2014 09:38:40 +0000 (+0800)
Subject: ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles
X-Git-Tag: v3.17-rc1~77^2~30^2~6
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=44991eb4bfd63b043b50e880d347a7946d6a9736;p=linux.git

ARM: dts: berlin2q: set L2CC tag and data latency to 2 cycles

For all BG2Q SoCs, 2 cycles is the best/correct value.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
---

diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 635a16a64cb4..3f95dc568b23 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -90,6 +90,8 @@ l2: l2-cache-controller@ac0000 {
 			compatible = "arm,pl310-cache";
 			reg = <0xac0000 0x1000>;
 			cache-level = <2>;
+			arm,data-latency = <2 2 2>;
+			arm,tag-latency = <2 2 2>;
 		};
 
 		scu: snoop-control-unit@ad0000 {