From: Linus Torvalds Date: Fri, 26 Jun 2015 18:34:35 +0000 (-0700) Subject: Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc X-Git-Tag: v4.2-rc1~100 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=4aa705b18bf17c4ff33ff7bbcd3f0c596443fa81;p=linux.git Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform support updates from Kevin Hilman: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits) ARM: zx: Add basic defconfig support for ZX296702 ARM: dts: zx: add an initial zx296702 dts and doc clk: zx: add clock support to zx296702 dt-bindings: Add #defines for ZTE ZX296702 clocks ARM: socfpga: fix build error due to secondary_startup MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS ARM: ep93xx: simone: support for SPI-based MMC/SD cards MAINTAINERS: update Shawn's email to use kernel.org one ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 ARM: EXYNOS: register power domain driver from core_initcall ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs ARM: SAMSUNG: Constify platform_device_id ARM: EXYNOS: Constify irq_domain_ops ARM: EXYNOS: add coupled cpuidle support for Exynos3250 ARM: EXYNOS: add exynos_get_boot_addr() helper ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ... --- 4aa705b18bf17c4ff33ff7bbcd3f0c596443fa81 diff --cc MAINTAINERS index 5f2956c24a9c,4052a5423a78..eaa131241298 --- a/MAINTAINERS +++ b/MAINTAINERS @@@ -1508,9 -1501,16 +1517,17 @@@ F: drivers/tty/serial/st-asc. F: drivers/usb/dwc3/dwc3-st.c F: drivers/usb/host/ehci-st.c F: drivers/usb/host/ohci-st.c +F: drivers/watchdog/st_lpc_wdt.c F: drivers/ata/ahci_st.c + ARM/STM32 ARCHITECTURE + M: Maxime Coquelin + L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) + S: Maintained + T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git + N: stm32 + F: drivers/clocksource/armv7m_systick.c + ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --cc arch/arm/mach-pxa/eseries.c index 4427bf26ea47,11863be59066..16dc95f68125 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c @@@ -10,9 -10,9 +10,10 @@@ * */ +#include #include #include + #include #include #include #include diff --cc arch/arm/mach-socfpga/core.h index 767c09e954a0,2484179c2b47..7259c3732702 --- a/arch/arm/mach-socfpga/core.h +++ b/arch/arm/mach-socfpga/core.h @@@ -31,8 -33,8 +33,6 @@@ #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ - extern void __iomem *socfpga_scu_base_addr; -extern void socfpga_secondary_startup(void); -- extern void socfpga_init_clocks(void); extern void socfpga_sysmgr_init(void); diff --cc arch/arm/mach-tegra/reset.h index 0aee0129f8d7,29c3dec0126a..9c479c7925b8 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@@ -35,7 -35,9 +35,8 @@@ extern unsigned long __tegra_cpu_reset_ void __tegra_cpu_reset_handler_start(void); void __tegra_cpu_reset_handler(void); + void __tegra20_cpu1_resettable_status_offset(void); void __tegra_cpu_reset_handler_end(void); -void tegra_secondary_startup(void); #ifdef CONFIG_PM_SLEEP #define tegra_cpu_lp1_mask \ diff --cc arch/arm/mach-zynq/common.h index 7038cae95ddc,f2f0bf2e7d14..79cda2e5fa4e --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@@ -17,9 -17,10 +17,8 @@@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ -void zynq_secondary_startup(void); - extern int zynq_slcr_init(void); extern int zynq_early_slcr_init(void); - extern void zynq_slcr_system_reset(void); extern void zynq_slcr_cpu_stop(int cpu); extern void zynq_slcr_cpu_start(int cpu); extern bool zynq_slcr_cpu_state_read(int cpu); diff --cc drivers/clk/Makefile index 9df871d53c6e,4dcbdd36f24e..5b6af6a9319f --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@@ -72,5 -73,5 +73,6 @@@ obj-$(CONFIG_ARCH_OMAP2PLUS) += ti obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/ obj-$(CONFIG_X86) += x86/ + obj-$(CONFIG_ARCH_ZX) += zte/ obj-$(CONFIG_ARCH_ZYNQ) += zynq/ +obj-$(CONFIG_H8300) += h8300/ diff --cc drivers/clocksource/Kconfig index d1bd53f2f360,618102e5aa2a..352b6a29910f --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@@ -276,10 -259,9 +276,15 @@@ config CLKSRC_PX This enables OST0 support available on PXA and SA-11x0 platforms. +config H8300_TMR16 + bool + +config H8300_TPU + bool + + config CLKSRC_IMX_GPT + bool "Clocksource using i.MX GPT" if COMPILE_TEST + depends on ARM && CLKDEV_LOOKUP + select CLKSRC_MMIO + endmenu diff --cc drivers/clocksource/Makefile index 2b344232262c,fce332cac646..e268b5e1901c --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@@ -54,7 -51,5 +54,8 @@@ obj-$(CONFIG_ARCH_KEYSTONE) += timer-k obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o + obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o +obj-$(CONFIG_H8300) += h8300_timer8.o +obj-$(CONFIG_H8300_TMR16) += h8300_timer16.o +obj-$(CONFIG_H8300_TPU) += h8300_tpu.o