From: Hyungwon Hwang <human.hwang@samsung.com>
Date: Fri, 12 Jun 2015 12:59:10 +0000 (+0900)
Subject: ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
X-Git-Tag: v4.2-rc1~13^2~8^2
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=4f01e65037187581971f8b1068d4e1b1300a6562;p=linux.git

ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'

The clock which was named as 'pll_clk' is actually not the clock source
of PLL in MIPI DSI. This patch fixes this disagreement.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e20cdc24c3bb..1538d7ae7b86 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -167,7 +167,7 @@ dsi_0: dsi@11C80000 {
 		phys = <&mipi_phy 1>;
 		phy-names = "dsim";
 		clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
-		clock-names = "bus_clk", "pll_clk";
+		clock-names = "bus_clk", "sclk_mipi";
 		status = "disabled";
 		#address-cells = <1>;
 		#size-cells = <0>;