From: Paul Walmsley <paul@pwsan.com>
Date: Sun, 23 Sep 2012 23:27:43 +0000 (-0600)
Subject: Merge branch 'clock_devel_3.7' into hwmod_prcm_clock_a_3.7
X-Git-Tag: v3.7-rc1~99^2~1^2^2~31
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=4fb85d35bcec842e0f20437aea277157973aa45f;p=linux.git

Merge branch 'clock_devel_3.7' into hwmod_prcm_clock_a_3.7

Conflicts:
	arch/arm/mach-omap2/clkt34xx_dpll3m2.c
	arch/arm/mach-omap2/clkt_clksel.c
	arch/arm/mach-omap2/clock.c
---

4fb85d35bcec842e0f20437aea277157973aa45f
diff --cc arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 298887b5bf66,0fd8b70201e4..7c6da2f731dc
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@@ -90,9 -92,10 +92,9 @@@ int omap3_core_dpll_m2_set_rate(struct 
  	if (c == 0)
  		c = 1;
  
- 	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- 		 validrate);
+ 	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+ 		 clkrate, validrate);
 -	pr_debug("clock: SDRC CS0 timing params used:"
 -		 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
 +	pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
  		 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
  		 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
  	if (sdrc_cs1)
diff --cc arch/arm/mach-omap2/clkt_clksel.c
index 19a980956d44,33382fb46cc1..eaed3900a83c
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@@ -357,11 -374,14 +374,13 @@@ void omap2_init_clksel_parent(struct cl
  				continue;
  
  			if (clkr->val == r) {
- 				if (clk->parent != clks->parent) {
+ 				if (parent != clks->parent) {
 -					pr_debug("clock: inited %s parent "
 -						 "to %s (was %s)\n",
 +					pr_debug("clock: %s: inited parent to %s (was %s)\n",
- 						 clk->name, clks->parent->name,
- 						 ((clk->parent) ?
- 						  clk->parent->name : "NULL"));
+ 						 clk_name,
+ 						 __clk_get_name(clks->parent),
+ 						 ((parent) ?
+ 						  __clk_get_name(parent) :
+ 						 "NULL"));
  					clk_reparent(clk, clks->parent);
  				};
  				found = 1;
diff --cc arch/arm/mach-omap2/dpll3xxx.c
index 27d79deb4ba2,02e74c1e62cf..814e1808e158
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@@ -617,17 -623,15 +623,18 @@@ unsigned long omap3_clkoutx2_recalc(str
  	unsigned long rate;
  	u32 v;
  	struct clk *pclk;
+ 	unsigned long parent_rate;
  
  	/* Walk up the parents of clk, looking for a DPLL */
- 	pclk = clk->parent;
+ 	pclk = __clk_get_parent(clk);
  	while (pclk && !pclk->dpll_data)
- 		pclk = pclk->parent;
+ 		pclk = __clk_get_parent(pclk);
  
 -	/* clk does not have a DPLL as a parent? */
 -	WARN_ON(!pclk);
 +	/* clk does not have a DPLL as a parent?  error in the clock data */
 +	if (!pclk) {
 +		WARN_ON(1);
 +		return 0;
 +	}
  
  	dd = pclk->dpll_data;