From: Ben Dooks Date: Sun, 24 Jun 2007 00:16:29 +0000 (-0700) Subject: SM501: Fix sm501_init_reg() mask/set order X-Git-Tag: v2.6.22-rc6~23 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=5136237bc392413332b02e69ada158c307da658f;p=linux.git SM501: Fix sm501_init_reg() mask/set order The order of the set and mask operation in sm501_init_reg() was setting and then masking the bits set. Correct the order so that we do not end up with 288MHz SDRAM clocks on certain systems. Signed-off-by: Ben Dooks Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- diff --git a/drivers/mfd/sm501.c b/drivers/mfd/sm501.c index 4c4412e0de24..3a0ecfc404e9 100644 --- a/drivers/mfd/sm501.c +++ b/drivers/mfd/sm501.c @@ -813,6 +813,9 @@ static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL); /* sm501_init_reg * * Helper function for the init code to setup a register + * + * clear the bits which are set in r->mask, and then set + * the bits set in r->set. */ static inline void sm501_init_reg(struct sm501_devdata *sm, @@ -822,8 +825,8 @@ static inline void sm501_init_reg(struct sm501_devdata *sm, unsigned long tmp; tmp = readl(sm->regs + reg); - tmp |= r->set; tmp &= ~r->mask; + tmp |= r->set; writel(tmp, sm->regs + reg); }