From: Akash Goel Date: Fri, 6 Mar 2015 05:37:17 +0000 (+0530) Subject: drm/i915/skl: Updated the gen6_set_rps function X-Git-Tag: v4.1-rc1~69^2~24^2~18 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=5704195c3f3c04a00c16334a033b180f16db1f94;p=linux.git drm/i915/skl: Updated the gen6_set_rps function On SKL, the frequency is programmed differently in RPNSWREQ (A008) register (from bits 23 to 31, compared to bits 24 to 31). So updated the gen6_set_rps function, as per this change. Signed-off-by: Akash Goel Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f240e8578e00..1f5583dc7e6f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3947,7 +3947,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) if (val != dev_priv->rps.cur_freq) { gen6_set_rps_thresholds(dev_priv, val); - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + if (IS_GEN9(dev)) + I915_WRITE(GEN6_RPNSWREQ, + GEN9_FREQUENCY(val)); + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(val)); else