From: Geert Uytterhoeven <geert+renesas@glider.be>
Date: Fri, 3 Mar 2017 13:18:17 +0000 (+0100)
Subject: arm64: dts: r8a7796: Remove unit-address and reg from integrated cache
X-Git-Tag: v4.12-rc1~52^2~22^2~11
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=57a4fd420c6e8a04b6a87ff24d34250cd7c48f15;p=linux.git

arm64: dts: r8a7796: Remove unit-address and reg from integrated cache

The Cortex-A57 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.

Fixes: 1561f20760ec96db ("arm64: dts: r8a7796: Add Renesas R8A7796 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index dbf82bc6ba64..27f7dd9bd988 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -47,9 +47,8 @@ a57_0: cpu@0 {
 			enable-method = "psci";
 		};
 
-		L2_CA57: cache-controller@0 {
+		L2_CA57: cache-controller-0 {
 			compatible = "cache";
-			reg = <0>;
 			power-domains = <&sysc R8A7796_PD_CA57_SCU>;
 			cache-unified;
 			cache-level = <2>;