From: Ville Syrjälä Date: Tue, 26 Mar 2019 14:25:55 +0000 (+0200) Subject: drm/i915: Update TRANS_MSA_MISC for fastsets X-Git-Tag: v5.2-rc1~118^2~34^2~9 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=5aa2c9ae9371326d9ee9199fe5dee072cc16c6a8;p=linux.git drm/i915: Update TRANS_MSA_MISC for fastsets Update the DP MSA MISC bits for fastsets. This is needed when we change between limited and full range RGB output. On HSW+ changing limited_range does not currently result in a full modeset since we have don't have the readout code for it (for DP we could, and probably should, readout from TRANS_MSA_MISC itself, for HDMI we would have to rely on the infoframe). So the PIPE_CONF_CHECK() is only performed for pre-HSW platforms. That means any change in the value will result in a fastset instead. Fortunately there is no prohibition to changing TRANS_MSA_MISC dynamically, so it looks like we can legally do fastsets for this. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20190326142556.21176-5-ville.syrjala@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index d33fe2952be3..3f1e491bd0c0 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3524,6 +3524,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder, { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + intel_ddi_set_pipe_settings(crtc_state); + intel_psr_update(intel_dp, crtc_state); intel_edp_drrs_enable(intel_dp, crtc_state);