From: James Hogan Date: Wed, 15 Jul 2015 15:17:45 +0000 (+0100) Subject: MIPS: dump_tlb: Only dump PageGrain if interesting X-Git-Tag: v4.3-rc1~85^2~89 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=5d3c3c7d296d9622560558de96875cf694d96f58;p=linux.git MIPS: dump_tlb: Only dump PageGrain if interesting The PageGrain register may not exist if certain architectural features aren't present, therefore only print out its value when dumping the TLB registers if it is expected to contain fields relevant to the TLB. Fixes: d1e9a4f54735 ("MIPS: Add SysRq operation to dump TLBs on all CPUs") Reported-by: Joshua Kinard Reported-by: Maciej W. Rozycki Signed-off-by: James Hogan Cc: Joshua Kinard Cc: Maciej W. Rozycki Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10723/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c index 519ededbf9a4..2ab83be14ffa 100644 --- a/arch/mips/lib/dump_tlb.c +++ b/arch/mips/lib/dump_tlb.c @@ -23,7 +23,8 @@ void dump_tlb_regs(void) pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0()); pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1()); pr_info("Wired : %0x\n", read_c0_wired()); - pr_info("PageGrain: %0x\n", read_c0_pagegrain()); + if (cpu_has_small_pages || cpu_has_rixi || cpu_has_xpa) + pr_info("PageGrain: %0x\n", read_c0_pagegrain()); if (cpu_has_htw) { pr_info("PWField : %0*lx\n", field, read_c0_pwfield()); pr_info("PWSize : %0*lx\n", field, read_c0_pwsize());