From: Oskar Senft Date: Thu, 5 Sep 2019 14:41:29 +0000 (-0400) Subject: dt-bindings: serial: 8250: Add aspeed,sirq-polarity-sense. X-Git-Tag: v5.5-rc1~54^2~51 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=6270d22d39022cc22cafc7ce4dd80114b6916710;p=linux.git dt-bindings: serial: 8250: Add aspeed,sirq-polarity-sense. Add documentation for 8250_aspeed_vuart's aspeed,sirq-polarity-sense property that enables to auto-configure the VUART's SIRQ polarity. Signed-off-by: Oskar Senft Acked-by: Rob Herring Link: https://lore.kernel.org/r/20190905144130.220713-2-osk@google.com Signed-off-by: Greg Kroah-Hartman --- diff --git a/Documentation/devicetree/bindings/serial/8250.txt b/Documentation/devicetree/bindings/serial/8250.txt index 20d351f268ef..55700f20f6ee 100644 --- a/Documentation/devicetree/bindings/serial/8250.txt +++ b/Documentation/devicetree/bindings/serial/8250.txt @@ -56,6 +56,11 @@ Optional properties: - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. It will use specified GPIO instead of the peripheral function pin for the UART feature. If unsure, don't specify this property. +- aspeed,sirq-polarity-sense: Only applicable to aspeed,ast2500-vuart. + phandle to aspeed,ast2500-scu compatible syscon alongside register offset + and bit number to identify how the SIRQ polarity should be configured. + One possible data source is the LPC/eSPI mode bit. + Example: aspeed,sirq-polarity-sense = <&syscon 0x70 25> Note: * fsl,ns16550: