From: Linus Walleij <linus.walleij@linaro.org>
Date: Thu, 29 Aug 2013 07:46:30 +0000 (+0200)
Subject: Merge tag 'v3.11-rc7' into devel
X-Git-Tag: v3.12-rc1~151^2~3
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=6ad30ce046aefbdc3848232c665a728860d7bb68;p=linux.git

Merge tag 'v3.11-rc7' into devel

Merged in this to avoid conflicts with the big locking fixes
from upstream.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Conflicts:
	drivers/pinctrl/pinctrl-sunxi.c
---

6ad30ce046aefbdc3848232c665a728860d7bb68
diff --cc drivers/pinctrl/pinctrl-sunxi.c
index 8dbd465b01d3,94716c779800..532202bbfc33
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@@ -282,48 -282,57 +283,51 @@@ static int sunxi_pconf_group_set(struc
  	u32 val, mask;
  	u16 strength;
  	u8 dlevel;
 +	int i;
  
 -	switch (pinconf_to_config_param(config)) {
 -	case PIN_CONFIG_DRIVE_STRENGTH:
 -		strength = pinconf_to_config_argument(config);
 -		if (strength > 40)
 -			return -EINVAL;
 -		/*
 -		 * We convert from mA to what the register expects:
 -		 *   0: 10mA
 -		 *   1: 20mA
 -		 *   2: 30mA
 -		 *   3: 40mA
 -		 */
 -		dlevel = strength / 10 - 1;
 -
 -		spin_lock_irqsave(&pctl->lock, flags);
 -
 -		val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
 -	        mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
 -		writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
 -			pctl->membase + sunxi_dlevel_reg(g->pin));
 -
 -		spin_unlock_irqrestore(&pctl->lock, flags);
 -		break;
 -	case PIN_CONFIG_BIAS_PULL_UP:
 -		spin_lock_irqsave(&pctl->lock, flags);
 -
 -		val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 -		mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 -		writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
 -			pctl->membase + sunxi_pull_reg(g->pin));
 -
 -		spin_unlock_irqrestore(&pctl->lock, flags);
 -		break;
 -	case PIN_CONFIG_BIAS_PULL_DOWN:
 -		spin_lock_irqsave(&pctl->lock, flags);
 -
 -		val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 -		mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 -		writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
 -			pctl->membase + sunxi_pull_reg(g->pin));
++	spin_lock_irqsave(&pctl->lock, flags);
+ 
 -		spin_unlock_irqrestore(&pctl->lock, flags);
 -		break;
 -	default:
 -		break;
 -	}
 +	for (i = 0; i < num_configs; i++) {
 +		switch (pinconf_to_config_param(configs[i])) {
 +		case PIN_CONFIG_DRIVE_STRENGTH:
 +			strength = pinconf_to_config_argument(configs[i]);
 +			if (strength > 40)
 +				return -EINVAL;
 +			/*
 +			 * We convert from mA to what the register expects:
 +			 *   0: 10mA
 +			 *   1: 20mA
 +			 *   2: 30mA
 +			 *   3: 40mA
 +			 */
 +			dlevel = strength / 10 - 1;
 +			val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
 +			mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
 +			writel((val & ~mask)
 +				| dlevel << sunxi_dlevel_offset(g->pin),
 +				pctl->membase + sunxi_dlevel_reg(g->pin));
 +			break;
 +		case PIN_CONFIG_BIAS_PULL_UP:
 +			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 +			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 +			writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
 +				pctl->membase + sunxi_pull_reg(g->pin));
 +			break;
 +		case PIN_CONFIG_BIAS_PULL_DOWN:
 +			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 +			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 +			writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
 +				pctl->membase + sunxi_pull_reg(g->pin));
 +			break;
 +		default:
 +			break;
 +		}
- 
 +		/* cache the config value */
 +		g->config = configs[i];
 +	} /* for each config */
  
 -	/* cache the config value */
 -	g->config = config;
++	spin_unlock_irqrestore(&pctl->lock, flags);
+ 
  	return 0;
  }