From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 14 Oct 2015 16:32:21 +0000 (+0800)
Subject: ARM: dts: sun8i: Add NMI interrupt controller node
X-Git-Tag: v4.4-rc1~51^2~32^2~3
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=6c067963f6e128bdca1e4db947f1a0e8ad2bd846;p=linux.git

ARM: dts: sun8i: Add NMI interrupt controller node

The NMI interrupt controller is in charge of the NMI pin exposed by
the SoC to the PMIC. The PMIC signals interrupts through this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 828aaf52c342..a1e3acd325f4 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -579,6 +579,14 @@ rtc: rtc@01f00000 {
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		nmi_intc: interrupt-controller@01f00c0c {
+			compatible = "allwinner,sun6i-a31-sc-nmi";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01f00c0c 0x38>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		prcm@01f01400 {
 			compatible = "allwinner,sun8i-a23-prcm";
 			reg = <0x01f01400 0x200>;