From: Lorenzo Pieralisi Date: Thu, 22 Mar 2018 16:33:17 +0000 (+0000) Subject: PCI: pcie-xilinx-nwl: Fix mask value to disable MSIs X-Git-Tag: v4.17-rc1~93^2~1^2 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=745029187a5465972fa2daf0fa43f1d2edb48de9;p=linux.git PCI: pcie-xilinx-nwl: Fix mask value to disable MSIs Compiling the xilinx-nwl driver with sparse checks result in the following warning: drivers/pci/host/pcie-xilinx-nwl.c:633:38: sparse: cast truncates bits from constant value (ffffffff00000000 becomes 0) Fix it by explicitly writing 0 to mask interrupts instead of relying on a bogus cast applied to the mask bitwise complement. Reported-by: Fengguang Wu Signed-off-by: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Rob Herring Cc: Michal Simek --- diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index 0acaf483d031..4839ae578711 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -630,7 +630,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) * For high range MSI interrupts: disable, clear any pending, * and enable */ - nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); + nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI); @@ -641,7 +641,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) * For low range MSI interrupts: disable, clear any pending, * and enable */ - nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); + nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);