From: Heiner Kallweit Date: Wed, 19 Sep 2018 20:00:24 +0000 (+0200) Subject: r8169: simplify RTL8169 PHY initialization X-Git-Tag: v4.20-rc1~27^2~315 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=7a67e11d901e17c3222d226c345be555106faae6;p=linux.git r8169: simplify RTL8169 PHY initialization PCI_LATENCY_TIMER is ignored on PCIe, therefore we have to do this for the PCI chips (version <= 06) only. Also we can move setting PCI_CACHE_LINE_SIZE. Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller --- diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index bb529ff2ca81..1b49d9e783f8 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -4048,16 +4048,13 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) rtl_hw_phy_config(dev); if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { + pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); + pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); netif_dbg(tp, drv, dev, "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); RTL_W8(tp, 0x82, 0x01); } - pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); - - if (tp->mac_version <= RTL_GIGA_MAC_VER_06) - pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); - if (tp->mac_version == RTL_GIGA_MAC_VER_02) { netif_dbg(tp, drv, dev, "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");