From: Stephen Warren Date: Fri, 20 Apr 2012 22:58:18 +0000 (-0600) Subject: ARM: tegra: fix pclk rate X-Git-Tag: v3.5-rc1~73^2~8^2~4 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=7ff4db0967bd7d617c77dc5a66c0d95166277817;p=linux.git ARM: tegra: fix pclk rate Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the rate of hclk. Since pclk is derived from that, and only has integer dividers, the pclk rate needs to change in the same fashion, from 54MHz to 60MHz. Signed-off-by: Stephen Warren --- diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index e96900418682..a4fba8835136 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -87,7 +87,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { { "pll_c_out1", "pll_c", 120000000, true }, { "sclk", "pll_c_out1", 120000000, true }, { "hclk", "sclk", 120000000, true }, - { "pclk", "hclk", 54000000, true }, + { "pclk", "hclk", 60000000, true }, { "csite", NULL, 0, true }, { "emc", NULL, 0, true }, { "cpu", NULL, 0, true },