From: Jisheng Zhang Date: Wed, 12 Nov 2014 06:22:52 +0000 (+0800) Subject: irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed X-Git-Tag: v3.19-rc1~156^2~2 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=8876ce7d1cbaca495bd6dee96d371f98e9cfb1eb;p=linux.git irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed There's no DMA at all, the device type memory attribute can ensure the operations order and relaxed version imply compiler barrier, so we are safe to use relaxed version to improve the performance a bit. Signed-off-by: Jisheng Zhang Acked-by: Sebastian Hesselbarth Link: https://lkml.kernel.org/r/1415773374-4629-2-git-send-email-jszhang@marvell.com Signed-off-by: Jason Cooper --- diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index 31e231e1f566..fcc338584bda 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -94,16 +94,16 @@ static int __init dw_apb_ictl_init(struct device_node *np, */ /* mask and enable all interrupts */ - writel(~0, iobase + APB_INT_MASK_L); - writel(~0, iobase + APB_INT_MASK_H); - writel(~0, iobase + APB_INT_ENABLE_L); - writel(~0, iobase + APB_INT_ENABLE_H); + writel_relaxed(~0, iobase + APB_INT_MASK_L); + writel_relaxed(~0, iobase + APB_INT_MASK_H); + writel_relaxed(~0, iobase + APB_INT_ENABLE_L); + writel_relaxed(~0, iobase + APB_INT_ENABLE_H); - reg = readl(iobase + APB_INT_ENABLE_H); + reg = readl_relaxed(iobase + APB_INT_ENABLE_H); if (reg) nrirqs = 32 + fls(reg); else - nrirqs = fls(readl(iobase + APB_INT_ENABLE_L)); + nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L)); domain = irq_domain_add_linear(np, nrirqs, &irq_generic_chip_ops, NULL);