From: Joel Stanley <joel@jms.id.au>
Date: Wed, 30 May 2018 06:17:40 +0000 (+0930)
Subject: ARM: dts: aspeed: Fix hwrng register address
X-Git-Tag: v4.18-rc1~50^2~1
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=927c2fc2db19fe6022be7c6dc0e380cb5c56a878;p=linux.git

ARM: dts: aspeed: Fix hwrng register address

The register address should be the full address of the rng, not the
offset from the start of the SCU.

Fixes: 5daa8212c08e ("ARM: dts: aspeed: Describe random number device")
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Olof Johansson <olof@lixom.net>
---

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 5e947ed496c2..75df1573380e 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -145,9 +145,9 @@ pinctrl: pinctrl {
 
 			};
 
-			rng: hwrng@78 {
+			rng: hwrng@1e6e2078 {
 				compatible = "timeriomem_rng";
-				reg = <0x78 0x4>;
+				reg = <0x1e6e2078 0x4>;
 				period = <1>;
 				quality = <100>;
 			};
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 24eec00c4a95..17f2714d18a7 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -189,9 +189,9 @@ pinctrl: pinctrl {
 				};
 			};
 
-			rng: hwrng@78 {
+			rng: hwrng@1e6e2078 {
 				compatible = "timeriomem_rng";
-				reg = <0x78 0x4>;
+				reg = <0x1e6e2078 0x4>;
 				period = <1>;
 				quality = <100>;
 			};