From: Icenowy Zheng Date: Sat, 25 Mar 2017 14:50:08 +0000 (+0800) Subject: dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 X-Git-Tag: v4.12-rc1~97^2~26^2~29 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=a0b1910e857897ae6c420fa0ece52c87d7cff373;p=linux.git dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. Signed-off-by: Icenowy Zheng Acked-by: Chen-Yu Tsai Signed-off-by: Kishon Vijay Abraham I --- diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index e42334258185..005bc22938ff 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -15,6 +15,7 @@ Required properties: - reg : a list of offset + length pairs - reg-names : * "phy_ctrl" + * "pmu0" for H3, V3s and A64 * "pmu1" * "pmu2" for sun4i, sun6i or sun7i - #phy-cells : from the generic phy bindings, must be 1