From: Stephen Boyd Date: Tue, 25 Jun 2019 00:40:40 +0000 (-0700) Subject: Merge tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson into clk-meson X-Git-Tag: v5.3-rc1~59^2~5^6 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=afa88bdbf19314494415d622d50730b5d854dd91;p=linux.git Merge tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson into clk-meson Pull Amlogic clk driver updates from Jerome Brunet: - Fix mpll fractional part and spread sprectrum issues - Add meson8 audio clocks - Add g12a temperature sensors clocks - Add g12a and g12b cpu clocks * tag 'clk-meson-5.3-1' of https://github.com/BayLibre/clk-meson: clk: meson: g12a: mark fclk_div3 as critical clk: meson: g12a: Add support for G12B CPUB clocks dt-bindings: clk: meson: add g12b periph clock controller bindings clk: meson-g12a: add temperature sensor clocks dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs clk: meson: meson8b: add the cts_i958 clock clk: meson: meson8b: add the cts_mclk_i958 clocks clk: meson: meson8b: add the cts_amclk clocks dt-bindings: clock: meson8b: add the audio clocks clk: meson: g12a: add controller register init clk: meson: eeclk: add init regs clk: meson: g12a: add mpll register init sequences clk: meson: mpll: add init callback and regs clk: meson: axg: spread spectrum is on mpll2 clk: meson: gxbb: no spread spectrum on mpll0 clk: meson: mpll: properly handle spread spectrum clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo --- afa88bdbf19314494415d622d50730b5d854dd91