From: Alexey Brodkin Date: Wed, 3 Oct 2012 12:27:43 +0000 (+0400) Subject: serial/8250/8250_early: Prevent rounding error in uartclk X-Git-Tag: v3.8-rc1~177^2~122 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=b15d5380e471f9ce27180b14d5080abc2e2f30ec;p=linux.git serial/8250/8250_early: Prevent rounding error in uartclk Modify divisor to select the nearest baud rate divider rather than the lowest. It minimizes baud rate errors especially on low UART clock frequencies. For example, if uartclk is 33000000 and baud is 115200 the ratio is about 17.9 The current code selects 17 (5% error) but should select 18 (0.5% error). This 5% error in baud rate leads to garbage on receiving end, while 0.5% doesn't. The issue showed up when using the stock 8250 driver for Synopsys DW UART. This was on a FPGA with ~12MHz UART clock. When we enabled early serial, we saw garbage which was narrowed down to the rounding error. So the bug had been latent and it only showed up with such low clock rates. Signed-off-by: Alexey Brodkin Acked-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/tty/serial/8250/8250_early.c b/drivers/tty/serial/8250/8250_early.c index eaafb98debed..843a150ba105 100644 --- a/drivers/tty/serial/8250/8250_early.c +++ b/drivers/tty/serial/8250/8250_early.c @@ -140,7 +140,7 @@ static void __init init_port(struct early_serial8250_device *device) serial_out(port, UART_FCR, 0); /* no fifo */ serial_out(port, UART_MCR, 0x3); /* DTR + RTS */ - divisor = port->uartclk / (16 * device->baud); + divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * device->baud); c = serial_in(port, UART_LCR); serial_out(port, UART_LCR, c | UART_LCR_DLAB); serial_out(port, UART_DLL, divisor & 0xff);