From: Venkata Narendra Kumar Gutta Date: Wed, 12 Sep 2018 18:06:35 +0000 (-0700) Subject: dt-bindings: msm: Update documentation of qcom,llcc X-Git-Tag: v4.20-rc1~64^2~7^2^2~31 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=b54ef3814f4a30c4c023ea099c8e4c962cfe3614;p=linux.git dt-bindings: msm: Update documentation of qcom,llcc Add reg-names and interrupts for LLCC documentation and the usage examples. llcc broadcast base is added in addition to llcc base, which is used for llcc broadcast writes. Signed-off-by: Venkata Narendra Kumar Gutta Reviewed-by: Rob Herring Signed-off-by: Andy Gross --- diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt index 5e85749262ae..eaee06b2d8f2 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -16,11 +16,26 @@ Properties: - reg: Usage: required Value Type: - Definition: Start address and the the size of the register region. + Definition: The first element specifies the llcc base start address and + the size of the register region. The second element specifies + the llcc broadcast base address and size of the register region. + +- reg-names: + Usage: required + Value Type: + Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base". + +- interrupts: + Usage: required + Definition: The interrupt is associated with the llcc edac device. + It's used for llcc cache single and double bit error detection + and reporting. Example: cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x250000>; + reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; };