From: Hoan Nguyen An Date: Fri, 24 Aug 2018 04:52:29 +0000 (+0900) Subject: clk: renesas: r8a77965: Add FDP clock X-Git-Tag: v4.20-rc1~49^2~12^2~1^2~1 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=bc7133cef81283d48a426604ef4af1507e2b20d9;p=linux.git clk: renesas: r8a77965: Add FDP clock This patch adds FDP1-0 clock to the R8A77965 SoC. Signed-off-by: Hoan Nguyen An Reviewed-by: Laurent Pinchart Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 312f9fe738e3..1fcc411502da 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { + DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1), DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),