From: Chen-Yu Tsai Date: Tue, 27 Jan 2015 19:54:08 +0000 (+0800) Subject: ARM: dts: sun9i: Add usb clock nodes to a80 dtsi X-Git-Tag: v4.2-rc1~99^2~48^2~78 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=bc8ffc2de87855f91b376dca4597ca0b9254cabc;p=linux.git ARM: dts: sun9i: Add usb clock nodes to a80 dtsi The USB controller and phy clocks and resets have a separate address block and driver. Add the nodes to represent them. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f0f6fb91f8c3..0ffecf6f91a9 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -137,6 +137,28 @@ osc32k: osc32k_clk { clock-output-names = "osc32k"; }; + usb_mod_clk: clk@00a08000 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-mod-clk"; + reg = <0x00a08000 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb0_ahb", "usb_ohci0", + "usb1_ahb", "usb_ohci1", + "usb2_ahb", "usb_ohci2"; + }; + + usb_phy_clk: clk@00a08004 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun9i-a80-usb-phy-clk"; + reg = <0x00a08004 0x4>; + clocks = <&ahb1_gates 1>; + clock-output-names = "usb_phy0", "usb_hsic1_480M", + "usb_phy1", "usb_hsic2_480M", + "usb_phy2", "usb_hsic_12M"; + }; + pll4: clk@0600000c { #clock-cells = <0>; compatible = "allwinner,sun9i-a80-pll4-clk";