From: Christoph Hellwig Date: Sat, 4 Aug 2018 08:23:15 +0000 (+0200) Subject: RISC-V: add a definition for the SIE SEIE bit X-Git-Tag: v4.19-rc1~88^2~7 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=bec2e6ac353d5c8a47c6eea639136bac3990093e;p=linux.git RISC-V: add a definition for the SIE SEIE bit This mirrors the SIE_SSIE and SETE bits that are used in a similar fashion. Signed-off-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 421fa3585798..28a0d1cb374c 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -54,6 +54,7 @@ /* Interrupt Enable and Interrupt Pending flags */ #define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ #define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */ +#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */ #define EXC_INST_MISALIGNED 0 #define EXC_INST_ACCESS 1