From: Bjorn Helgaas <bhelgaas@google.com>
Date: Tue, 16 Jun 2015 13:19:55 +0000 (-0500)
Subject: Merge branches 'pci/host-designware', 'pci/host-designware-common', 'pci/host-generic... 
X-Git-Tag: v4.2-rc1~155^2~2
X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=bf933dbb84453c502355743828a37ead5e82aa68;p=linux.git

Merge branches 'pci/host-designware', 'pci/host-designware-common', 'pci/host-generic', 'pci/host-imx6', 'pci/host-iproc' and 'pci/host-xgene' into next

* pci/host-designware:
  PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM
  PCI: designware: Consolidate outbound iATU programming functions
  PCI: designware: Add support for x8 links

* pci/host-designware-common:
  PCI: designware: Wait for link to come up with consistent style
  PCI: layerscape: Factor out ls_pcie_establish_link()
  PCI: layerscape: Use dw_pcie_link_up() consistently
  PCI: dra7xx: Use dw_pcie_link_up() consistently
  PCI: imx6: Rename imx6_pcie_start_link() to imx6_pcie_establish_link()

* pci/host-generic:
  of/pci: Fix pci_address_to_pio() conversion of CPU address to I/O port

* pci/host-imx6:
  PCI: imx6: Add #define PCIE_RC_LCSR
  PCI: imx6: Use "u32", not "uint32_t"
  PCI: imx6: Add speed change timeout message

* pci/host-iproc:
  PCI: iproc: Free resource list after registration
  PCI: iproc: Directly add PCI resources
  PCI: iproc: Add BCMA PCIe driver
  PCI: iproc: Allow override of device tree IRQ mapping function

* pci/host-xgene:
  arm64: dts: Add APM X-Gene PCIe MSI nodes
  PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination driver
---

bf933dbb84453c502355743828a37ead5e82aa68
diff --cc drivers/pci/host/pci-imx6.c
index fdb95367721e,fdb95367721e,af7da8ac8082,fdb95367721e,a4ee579421df,fdb95367721e,fdb95367721e..233a196c6e66
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@@@@@@@ -335,23 -335,23 -335,21 -335,23 -337,40 -335,23 -335,23 +337,38 @@@@@@@@ static void imx6_pcie_init_phy(struct p
       
       static int imx6_pcie_wait_for_link(struct pcie_port *pp)
       {
-- ----	int count = 200;
++ ++++	unsigned int retries;
       
-- ----	while (!dw_pcie_link_up(pp)) {
++ ++++	for (retries = 0; retries < 200; retries++) {
++ ++++		if (dw_pcie_link_up(pp))
++ ++++			return 0;
       		usleep_range(100, 1000);
-- ----		if (--count)
-- ----			continue;
-- ----
-- ----		dev_err(pp->dev, "phy link never came up\n");
-- ----		dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
-- ----			readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
-- ----			readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
-- ----		return -EINVAL;
       	}
       
-- ----	return 0;
++ ++++	dev_err(pp->dev, "phy link never came up\n");
++ ++++	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
++ ++++		readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
++ ++++		readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
++ ++++	return -EINVAL;
++ + ++}
++ + ++
++++ ++static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
++++ ++{
++++ ++	u32 tmp;
++++ ++	unsigned int retries;
++++ ++
++++ ++	for (retries = 0; retries < 200; retries++) {
++++ ++		tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
++++ ++		/* Test if the speed change finished. */
++++ ++		if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
++++ ++			return 0;
++++ ++		usleep_range(100, 1000);
++++ ++	}
++++ ++
++++ ++	dev_err(pp->dev, "Speed change timeout\n");
++++ ++	return -EINVAL;
  +    }
  +    
       static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
       {
       	struct pcie_port *pp = arg;
@@@@@@@@ -359,11 -359,11 -357,11 -359,11 -378,11 -359,11 -359,11 +376,11 @@@@@@@@
       	return dw_handle_msi_irq(pp);
       }
       
-- ----static int imx6_pcie_start_link(struct pcie_port *pp)
++ ++++static int imx6_pcie_establish_link(struct pcie_port *pp)
       {
       	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
---- --	uint32_t tmp;
---- --	int ret, count;
++++ ++	u32 tmp;
++++ ++	int ret;
       
       	/*
       	 * Force Gen1 operation when starting the link.  In case the link is