From: Jordan Crouse Date: Tue, 21 Nov 2017 19:40:57 +0000 (-0700) Subject: drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter X-Git-Tag: v4.16-rc1~96^2~8^2~1 X-Git-Url: https://asedeno.scripts.mit.edu/gitweb/?a=commitdiff_plain;h=c09513cfebd8d936a7aed3c0302104fb47a4a03a;p=linux.git drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter Even though the default countable for CP0 is CP_ALWAYS_COUNT (0), program the selector during HW initialization in an effort to be up front about which counters are programmed and why. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark --- diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index fdbe9e9bb2b1..56c2c441fabf 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -597,6 +597,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* Turn on performance counters */ gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); + /* Select CP0 to always count cycles */ + gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); + /* Increase VFD cache access so LRZ and other data gets evicted less */ gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);